In this paper, we present two important topics indirectly related to the design and simulated analysis of NETWORK-on-Chip (NoC) architectures. In order to enhance the performance of the baseline router to achieve maximum throughput, a new parallel buffer architecture and its management scheme are introduced. By adopting an adjustable architecture that integrates a parallel buffer with each incoming port, the design complexity and its utilization can be optimized. By utilizing simulation-based performance evaluation and comparison with previous NoC architectures, its efficiency and superiority are proven. One of the key areas of research addressed in this work is to find more realistic traffic models in order to properly test the buffer management schemes proposed in this work. Therefore, we introduce a generic traffic model for on-chip INTERCONNECTION NETWORKs that is superior to previous techniques for NoC architectural performance evaluation. Our traffic model is based on three empirically-derived statistical characteristics using temporal and spatial distributions. With captured parameters, accurate traffic patterns can be generated recursively to show similar statistical characteristics of the observed on-chip NETWORKs.